1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including transistor elements comprising highly capacitive gate structures on the basis of a metal-containing electrode material and a high-k gate dielectric of increased permittivity compared to conventional gate dielectrics, such as silicon dioxide and silicon nitride.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode, to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with thermal design power requirements for performance driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Therefore, it has been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3) having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance based on the same thickness as a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since, typically, a low threshold voltage of the transistor, which represents the voltage at which a conductive channel forms in the channel region, is desired to obtain the high drive currents, the controllability of the respective channel requires pronounced lateral dopant profiles and dopant gradients, at least in the vicinity of the PN junctions. Therefore, so-called halo regions are usually formed by ion implantation in order to introduce a dopant species whose conductivity type corresponds to the conductivity type of the remaining channel and semiconductor region to “reinforce” the resulting PN junction dopant gradient after the formation of respective extension and deep drain and source regions. In this way, the threshold voltage of the transistor significantly determines the controllability of the channel, wherein a significant variance of the threshold voltage may be observed for reduced gate lengths. Hence, by providing an appropriate halo implantation region, the controllability of the channel may be enhanced, thereby also reducing the variance of the threshold voltage, which is also referred to as threshold roll-off, and also reducing significant variations of transistor performance with a variation in gate length. Since the threshold voltage of the transistors is significantly determined by the work function of the metal-containing gate material, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
After forming sophisticated gate structures including a high-k dielectric and a metalbased gate material, however, high temperature treatments may be required, which may result in a reduction of the permittivity of the gate dielectric caused by an increase of the oxygen contents in the high-k material, thereby also resulting in an increase of layer thickness. Furthermore, a shift of the work function may be observed which is believed to be associated with the enhanced oxygen affinity of many high-k dielectric materials, resulting in a redistribution of oxygen from trench isolation structure via the high-k dielectric material of shared gate line structures, in particular at the moderately high temperatures required for completing the transistors after forming the high-k metal gate structure. Due to this Fermi level shift in the metal-containing gate materials, the resulting threshold voltage may become too high to enable the use of halo implantation techniques for adjusting the transistor characteristics with respect to controlling threshold voltage roll-off to allow high drive current values at moderately low threshold voltages.
The moderate and high temperatures during the transistor fabrication process may be avoided by using an integration scheme, in which the gate electrode structure is formed according to conventional techniques and is finally replaced by a sophisticated high-k metal gate structure, wherein the respective metals are appropriately selected so as to have suitable work functions for N-channel transistors and P-channel transistors, respectively. Thus, in this integration scheme, the conventional polysilicon/oxide gate structure is removed and replaced by the high-k metal stack after the final high temperature anneal processes and the silicidation of the drain and source regions. Hence, the high-k metal gate electrode structure may only experience low temperatures used in the back-end processing, that is, temperatures of approximately 400° C., thereby substantially avoiding the above-described problems with respect to altering the characteristics of the high-k material and shifting the work functions of the metals in the gate electrodes.
Consequently, the replacement of the polysilicon/silicon dioxide gate electrode structure in a very advanced manufacturing stage of the transistor, i.e., after any high temperature processes, is a very promising approach for fabricating transistor elements with enhanced gate electrode structures. Due to these advantages, however, a certain degree of defects may be observed in sophisticated applications, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a semiconductor device 100 in the form of a transistor element in an advanced manufacturing stage. As previously explained, the transistor 100 may comprise drain and source regions 111 formed in a corresponding portion of a semiconductor layer 102. The semiconductor layer 102 may be a part of a substantially crystalline material of a substrate 101, typically a silicon substrate, or the semiconductor layer 102 may be formed on a buried insulating layer (not shown), when an SOI configuration is considered. Moreover, above a channel region 112, a gate electrode structure 110 is formed, which is to be understood as a placeholder structure since essential portions thereof are to be removed in a later manufacturing stage. As illustrated, the gate electrode structure 110 typically comprises a gate dielectric material 110A formed on the channel region 112 and typically comprised of silicon dioxide, which may have a thickness that is appropriate for acting as a gate dielectric material in other device regions in which less critical performance requirements may have to be met. For example, the gate dielectric material 110A may represent a silicon dioxide layer with a thickness of 2 nm and more. Furthermore, a polysilicon material 110B is formed on the gate dielectric layer 110A in accordance with well-established device architecture. Additionally, due to the advanced manufacturing stage of the device 100, metal silicide material 110C is typically formed in an upper portion of the polysilicon material 110B, and corresponding metal silicide regions 113 may also be provided in the drain and source regions. The gate electrode structure 110 may further comprise a spacer structure 110D, for instance in the form of an etch stop liner 110E and a spacer element 110F, which are typically comprised of silicon dioxide and silicon nitride, respectively. Furthermore, a first dielectric layer 103, for instance in the form of a silicon nitride material and the like, is typically formed above the gate electrode structure 110 and the drain and source regions 111, wherein a more or less pronounced internal stress level may be provided in the layer 103, depending on the overall process strategy. As is well known, inducing a specific strain component in the channel region 112 may result in a corresponding lattice distortion, which in turn may modify the charge carrier mobility therein. By applying the layer 103 with a moderately high internal stress level, a desired type of strain may therefore be created in the channel region 112, if desired. Moreover, an interlayer dielectric material 104 in the form of silicon dioxide is formed above the layer 103.
Typically, the semiconductor device 100 is formed on the basis of the following process strategy. After defining corresponding active regions (not shown) in the semiconductor layer 102, a basic dopant profile may be established, for instance by implantation techniques, thereby defining the conductivity of corresponding transistor elements. Thereafter, the material of the gate dielectric layer 110A and the gate electrode material 110B may be formed, for instance, by performing well-established oxidation processes and the like, followed by the deposition of the polysilicon material on the basis of well-established low pressure chemical vapor deposition (CVD) techniques. Thereafter, sophisticated lithography and etch processes may be performed in order to provide an appropriate etch mask that substantially determines the lateral dimension of the gate electrode structure 110, i.e., of the corresponding polysilicon material. During the complex patterning process, a process inherent profile of the gate electrode material 110B may be generated due to the nature of the corresponding etch processes, which may result in a certain degree of corner rounding and the like of the etch mask, thereby also creating a tapering of the polysilicon material. In sophisticated applications in which a gate length of 50 nm and less is to be established, the corresponding degree of tapering may result in a variation of gate length from top to bottom, as indicated by 110T and 110L, respectively. For example, for an effective gate length, i.e., the length 110L, of approximately 45 nm, the corresponding gate length at the top of the structure 110, i.e., the length 110T, may be less by approximately 25% and even more for a typical gate height of approximately 80-100 nm, as may be required for obtaining the desired ion blocking effect of the gate electrode structure 110. A corresponding pronounced degree of tapering may, however, have a negative effect in a later manufacturing stage when the materials 110A, 110B, in combination with metal silicide material 110C, are to be replaced by a high-k dielectric material and a metal-containing gate electrode material.
After patterning the polysilicon material, the further processing may be continued by forming appropriate offset spacers and incorporating dopant species as required for establishing a desired dopant profile connecting to the channel region 112. Furthermore, further implantation processes may be performed on the basis of a more or less advanced stage of the spacer structure 110D, thereby finally obtaining the overall dopant profile for the drain and source regions 111. Thereafter, any final high temperature processes may be performed, for instance for activating dopants and re-crystallizing implantation-induced damage. Consequently, during the entire process sequence, the well-known and well-established characteristics of the polysilicon material 110B in combination with the silicon dioxide based gate dielectric material 110A may provide a reliable process sequence. Thereafter, the dielectric material 103 is deposited, for instance, by plasma enhanced CVD techniques, followed by the deposition of the material 104, for instance in the form of a silicon dioxide material. Next, a chemical mechanical polishing (CMP) process 105 is typically performed in order to remove material of the layers 104, 103 thereby exposing the gate electrode structure 110.
FIG. 1b schematically illustrates the transistor 100 in a further advanced manufacturing stage. As illustrated, a top surface 110S of the gate electrode structure 110 is exposed, for instance by the previously performed planarization process 105 (FIG. 1a), thereby also removing a portion of the metal silicide material 110C. Next, the gate electrode material 110B and the residue of metal silicide material 110C are removed, for instance on the basis of a wet chemical etch process 106, which may be performed on the basis of an etch chemistry having a high selectivity between silicon material and silicon dioxide and silicon nitride. For example, a plurality of appropriate wet chemical etch chemistries are available, such as TMAH (tetra methyl ammonium hydroxide) which may be used at an elevated temperature of approximately 50-80° C. In this case, TMAH, when provided in higher concentrations, has an excellent selectivity with respect to silicon dioxide and silicon nitride while efficiently removing silicon material. Consequently, after etching through the remaining portion of the metal silicide region 110C, the polysilicon material 110B may be efficiently removed. Thereafter, a further etch process is typically applied in order to remove the silicon dioxide based gate dielectric material 110A, which may be accomplished on the basis of hydrofluoric acid and the like. Consequently, after removing the materials 110B and 110A, a high-k dielectric material in combination with a metal-containing electrode material may be deposited in order to obtain the gate electrode structure 110 with enhanced performance.
FIG. 1c schematically illustrates the device 100 during a process sequence in which a high-k dielectric material 115, for instance hafnium oxide and the like, is deposited with a desired thickness, for instance 10-25 Å in sophisticated applications, followed by the deposition of a metal-containing electrode material 116, for instance in the form of titanium nitride and the like. In particular, during the deposition of the metal-containing material 116, the inverse tapering of the opening formed during the removal of the gate electrode material 110B (FIG. 1b) may result in deposition-related non-uniformities, for instance in the form of voids 116A and the like, which may result in reduced reliability and in a complete gate failure, thereby contributing to increased yield losses.
Consequently, although the replacement of a conventional gate electrode structure by sophisticated high-k dielectrics and metal-containing electrode materials in a very advanced manufacturing stage may be advantageous in view of reliability of the high-k dielectric material and the gate electrode material, the tapering of the previously formed polysilicon placeholder material may contribute to a significant reliability issue, so that the conventional strategy described above is less desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.